Interfacing requirements for MEMS components in system-on-chip methodologies

Modern VLSI design is moving towards a System-on-Chip design paradigm, where chip design involves the integration of separate macrocells from different manufacturers. This paper explores the obstacles to adopting this same methodology for systems incorporating MEMS components. These obstacles include the technology specific nature of most MEMS devices, interference between MEMS sensors, and the limited electronics device density of mixed MEMS/Microelectronics technologies. It is conjectured that one fruitful avenue for further work is the development of MEMS interface circuits which can be incorporated into a single SoC along with other electronics macrocells, and which men connect to discrete MEMS sensor chips

Measuring a coherent superposition

We propose a simple method for measuring the populations and the relative phase in a coherent superposition of two atomic states. The method is based on coupling the two states to a third common (excited) state by means of two laser pulses, and measuring the total fluorescence from the third state for several choices of the excitation pulses.Comment: 7 pages, 1 figure, twocolumn REVTe

Egret: A platform for reconfigurable system-on-chip

Reconfigurable System-on-Chip (rSoC) design is inherently a complex task with enormous freedom in design parameters such as processor, operating system, and backplane buses. Design efficiency can be improved by the use of an rSoC platform which constrains these choices, and allows new designs to leverage much of the expertise of previous designs. Egret is an rSoC prototyping platform being developed at the University of Queensland, Australia, and this paper explains and justifies the design decisions for the first version of Egret

Hardware support for real-time reconfigurable system-on-chip

This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented at run-time in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communication is described, along with how this is affected by dynamic configuration. Some research goals are identified, including investigating the effects on real-time performance, power consumption and the design process involved in reconfigurable systems

Interfacing methodologies for IP re-use in reconfigurable system-on-chip

Initially, IP cores in Systems-on-Chip were interconnected through custom interface logic. The more recent use of standard on-chip buses has eased integration and eliminated inefficient glue logic, and hence boosted the production of IP functional cores. However, once an IP block is designed to target a particular on-chip bus standard, retargeting to a different bus is time-consuming and tedious. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new methodology is presented that can automate the connection of an IP block to a wide variety of interface architectures with low overhead through the use a special Interface Adaptor Logic layer

On-chip interconnect schemes for reconfigurable system-on-chip

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses

Effect of current corrugations on the stability of the tearing mode

The generation of zonal magnetic fields in laboratory fusion plasmas is predicted by theoretical and numerical models and was recently observed experimentally. It is shown that the modification of the current density gradient associated with such corrugations can significantly affect the stability of the tearing mode. A simple scaling law is derived that predicts the impact of small stationary current corrugations on the stability parameter $\Delta'$. The described destabilization mechanism can provide an explanation for the trigger of the Neoclassical Tearing Mode (NTM) in plasmas without significant MHD activity.Comment: Accepted to Physics of Plasma

FIFO Communication Models in Operating Systems for Reconfigurable Computing

Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating systems such as embedded Linux. In reconfigurable System-on-Chip (rSoC) design, a critical issue is efficient integration of custom hardware and software resources, where efficiency must be considered in terms of both design time and run time. Process networks communicating via FIFO queues are a powerful model for real time digital system design, especially for data streaming applications such as multimedia devices. FIFOs also form a central part of Unix and Linux Interprocess Communication (IPC) architectures, where they are more commonly known as pipes. In this paper, we expand on this observation and show how the combination of embedded Linux, reconfigurable System-on-Chip, and FIFO communication models provide a compelling platform for efficient design- and run-time implementation of complex, high performance embedded systems

Coherent properties of a tripod system coupled via a continuum

We present results from a study of the coherence properties of a system involving three discrete states coupled to each other by two-photon processes via a common continuum. This tripod linkage is an extension of the standard laser-induced continuum structure (LICS) which involves two discrete states and two lasers. We show that in the tripod scheme, there exist two population trapping conditions; in some cases these conditions are easier to satisfy than the single trapping condition in two-state LICS. Depending on the pulse timing, various effects can be observed. We derive some basic properties of the tripod scheme, such as the solution for coincident pulses, the behaviour of the system in the adiabatic limit for delayed pulses, the conditions for no ionization and for maximal ionization, and the optimal conditions for population transfer between the discrete states via the continuum. In the case when one of the discrete states is strongly coupled to the continuum, the population dynamics reduces to a standard two-state LICS problem (involving the other two states) with modified parameters; this provides the opportunity to customize the parameters of a given two-state LICS system